1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of a split-gate semiconductor device, such as an electrically programmable read-only semiconductor memory device.
2. Description of the Related Art
Nonvolatile memory or storage devices, such as electrically erasable, programmable read-only memories (EEPROMs), are an important element in the design of electronic devices, such as computers, telecommunications hardware and consumer appliances. A nonvolatile memory (NVM) device is typically constructed with a plurality of cells, each of which is formed as a field effect transistor (FET) which includes a separate charge storage element for storing electrical charge (holes or electrons). For example, a floating-gate NVM cell is characterized by a stacked gate construction in which a floating gate, typically formed from polysilicon, is separated from the substrate by a first (lower) oxide layer and is separated from a polysilicon control gate by a second (upper) oxide layer. No direct electrical connection is made to the floating gate (hence, “floating”). A split-gate NVM cell typically exhibits two distinguishable channel regions, respectively controllable by the floating gate and the control gate, which may or may not be partially overlapping. In whatever configuration is used, data is stored in an NVM cell by modulating the threshold voltage, VT, of the FET through the injection of charge carriers through a dielectric layer and into the charge storage element.
Split-gate NVM cells may advantageously be constructed to include a plurality of nanoclusters (a.k.a. nanocrystals) in the dielectric layer which function to store charge in the dielectric layer. When the control gate is formed before the select gate, the nanoclusters may be formed in the dielectric layer between the control gate and the substrate by (1) growing or depositing a first dielectric layer (e.g., silicon dioxide) over the substrate in the NVM cell channel region, (2) depositing nanocrystals on the first dielectric layer, (3) depositing a second dielectric layer (e.g., silicon dioxide) over the first dielectric layer and nanocrystals and (4) heating the nanocrystals and dielectric layers. When the select gate is formed subsequently (e.g., by forming a third dielectric layer over the control gate and substrate and then forming an etched select gate thereon which is separated from the control gate by the third dielectric layer on the sidewall of the control gate), the resulting split-gate NVM cell structure does not include charge storage nanocrystals in the gap dielectric between the control gate and select gate. However, when the select gate is formed before the control gate (e.g., by forming a gap dielectric layer with nanocrystals over the select gate and substrate and then forming an etched control gate thereon which is separated from the select gate by the gap dielectric layer on the sidewall of the select gate), the resulting split-gate NVM cell structure includes charge storage nanocrystals in the gap between the control gate and select gate, and also in the dielectric layer between the control gate and the substrate.
While there are performance and programming benefits of forming split-gate NVM cells by forming the select gate before control gate first, there are drawbacks associated with the presence of nanocrystals being formed in the gap dielectric between the select gate and control gate or near the control gate corner. For example, load-up effects can be created by the presence of nanocrystals in the gap dielectric, and to some extent, by the presence of any nanocrystal(s) near the control gate corner due to the corner geometry. For example, with a bottom erase (negative gate erase) technology, the load-up effect is caused by the large electric fields which permit electrons to be injected into the corner-region nanocrystals. With top erase (positive gate erase) technology, the corner geometry prevents the gate from removing charge that has accumulated in the corner nanocrystals. In addition, strong corner-region nanocrystal effects may lead to device variation in narrow width devices due to the random nature of nanocrystal formation. In addition to gap nanocrystals effects, trap-up effects may occur in the dielectric near the control gate corner. For example, with a bottom erase technology, a trap-up effect may occur when large electric fields cause electron injection into oxide traps.
Accordingly, a need exists for a semiconductor manufacturing process and apparatus which eliminates or reduces the effects of nanocrystals or oxide traps being formed in the gap dielectric of a split-gate NVM cell. In addition, there is a need for a fabrication process which addresses the load-up, trap-up and or fluctuation effects caused by charging of nanocrystals formed in the gap dielectric of a split-gate device. There is also a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.